si9150 vishay siliconix document number: 70020 s-40752?rev. f, 19-apr-04 www.vishay.com 1 synchronous buck converter controller features 6- to 16.5-v input range (si9150cy) voltage-mode pwm control low-current standby mode enable control dual 100-ma output drivers 2% band gap reference multiple converters easily synchronized over-current protection description the si9150 synchronous buck regulator controller is ideally suited for high-efficiency step down converters in battery-powered equipment. combined with the si9943dy mosfet half-bridge, a 90% efficient, 7.5-w, 3.3-v or 5-v power supply can be implemented using standard surface- mount assembly techniques. the wide input range allows operation from nicd or nimh battery packs using six to ten cells. over-current protection is achieved by sensing the on-state voltage drop across the high side p-channel mosfet, which eliminates the need for a current sense resistor. duty ratios of 0 to 100% and switching frequencies up to 300 khz are possible. the ic can be disabled by pulling en low (i dd = 100 a), or the 2.5-v reference can be maintained, with all other functions disabled, by pulling stby low (i dd = 500 a). the si9150 is available in both standard and lead (pb)-free 14-pin soic and rated for the commercial temperature range of 0 to 70 c (c suffix), and the industrial temperature range of ? 40 to +85 c (d suffix). functional block diagram synchronous buck regulator controller stby ss gnd i sense ? + 0.5 v v dd en p-gate r q s oscillator, comparators, & error amp reference generator power down uvlo ? + + ? ref gen osc r q s break- before- make logic n-gate 1 v sync c t r t comp fb v ref error amplifier 4.7 v 500 k strobe v dd current limit 1 2 3 4 5 6 7 8 910 11 12 13 14 20 a 5 w
si9150 vishay siliconix www.vishay.com 2 document number: 70020 s-40752?rev. f, 19-apr-04 absolute maximum ratings voltages referenced to gnd. v dd 18 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i sense input ? 2 v to v dd +2 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . all other inputs ? 0.3 to v dd + 0.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . p-gate, n-gate continuous source/sink current 50 ma . . . . . . . . . . . . . . . . storage temperature ? 65 to 125 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . operating junction temperature 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . power dissipation (package)a 14-pin soic (y suffix) b 900 mw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . thermal impedance ( ja ) 14-pin soic 140 c/w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . notes a. device mounted with all leads soldered or welded to pc board. b. derate 7.2 mw/ c. specifications a test conditions unless otherwise specified limits c suffix 0 to 70 c limits d suffix ? 40 to 85 c parameter symbol unless otherwise specified 6.0 v dd 16.5 v min b typ c max b min b typ c max b unit reference output voltage v ref t a = 25 c measured at feedback e pin 5 2.45 2.50 2.55 2.45 2.50 2.55 v output voltage v ref t min to t max d 2.425 2.500 2.575 2.40 2.500 2.60 v oscillator maximum frequency f max c osc =94.3 pf, r osc = 28.7 k t a = 25 c f 255 300 345 255 300 345 khz initial accuracy f osc c osc =212 pf, r osc = 41.2 k t a = 25 c f 85 100 115 85 100 115 kh z oscillator ramp amplitude v osc t a = 25 c, 100 khz 2.05 2.65 2.85 2.05 2.65 2.85 v temperature stability d f temp v dd = 10 v, t min to t max ? 5 3 +5 ? 6 4 +6 % error amplifier input bias current i b v fb = v ref 25 500 25 750 na open loop voltage gain d a vol 60 72 58 72 db offset voltage v os 10 25 10 30 mv unity gain bandwidth d bw 1 1.5 1 1.5 mhz output current i out source, v comp = 2.50 v ? 0.30 ? 0.20 ? 0.30 ? 0.15 ma output current i out sink, v comp = 1.0 v 1 2.5 0.9 2.5 ma power supply rejection psrr 50 70 48 70 db protection current limit threshold voltage v cl t a = 25 c, v dd = 10 v 0.43 0.49 0.55 0.43 0.49 0.55 v current limit delay to output d t d t a = 25 c 500 1000 500 1000 ns undervoltage lockout voltage v uvlo upper threshold 5.4 5.7 6.0 5.38 5.7 6.01 v undervoltage hysteresis v hys 0.10 0.17 0.25 0.10 0.17 0.26 v softstart pull-up current i ss 20 20 a supply supply current (enable low) i off 60 100 60 100 a supply current (enable high) i cc c l = 0 pf, f osc = 100 khz v dd = 10 v 2.2 3.0 2.2 3.0 ma supply current (stby low) i sb 300 500 300 550 a
si9150 vishay siliconix document number: 70020 s-40752?rev. f, 19-apr-04 www.vishay.com 3 specifications a limits d suffix ? 40 to 85 c limits c suffix 0 to 70 c test conditions unless otherwise specified 6.0 v dd 16.5 v parameter unit max b typ c min b max b typ c min b test conditions unless otherwise specified 6.0 v dd 16.5 v symbol output output high voltage v oh i out = 10 ma, v dd = 10 v 9.75 9.7 v output low voltage v ol i out = ? 10 ma, v dd = 10 v 0.25 0.3 v output resistance r out i out = 100 ma, v dd = 10 v 10 20 10 25 rise time d t r c l = 800 pf v dd = 10 v 30 60 30 70 ns fall time d t f c l = 800 pf, v dd = 10 v 30 60 30 70 ns logic delay to output t d(en) transition high to low 0.25 1 0.25 1 s enable pull-up resistance r en 500 500 k stby pull-up current i stby t a = 25 c, v stby = 0 v v dd = 10 v ? 25 ? 20 ? 15 ? 28 ? 20 ? 12 a turn-on threshold v enh v dd = 10 v, rising input voltage 6 6.8 8 6 6.8 8 v turn-off threshold v enl v dd = 10 v, falling input voltage 2 3.75 5 2 3.75 5 v notes a. refer to process option flowchart for additional information. b. the algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data s heet. c. typical values are for design aid only, not guaranteed nor subject to production testing. d. guaranteed by design, not subject to production test. e. the voltage reference is trimmed with the feedback (pin 5) connected to compensation (pin 4) so that the effect of the error amplifier?s input offset voltage is eliminated. f. c osc includes the pc board?s parasitic capacitance. typical characteristics (25 c unless otherwise noted) oscillator characteristics 10 100 1000 1000 100 10 50 pf 100 pf 150 pf 200 pf frequency (khz) r osc ? oscillator resistance (k )
en v dd standby soic p-gate ss n-gate comp gnd fb v ref i sense r t c t sync top view 11 12 13 14 2 3 4 1 8 9 10 5 6 7 si9150 vishay siliconix www.vishay.com 4 document number: 70020 s-40752?rev. f, 19-apr-04 pin configuration and ordering information ordering information part number temperature range package si9150cy si9150cy-t1 0 to 70 c si9150cy-t1?e3 soic - 14 si9150dy soic - 1 4 si9150dy-t1 ? 40 to 85 c si9150dy-t1?e3 40 to 85 c pin description pin 1: en when this pin is low, the ic is shut down. after a low signal is applied to en, then comp, ref, r t , and c t settle toward ground; n-gate, stby and soft-start are grounded; and p-gate is pulled high. the current consumption is no more than 100 a in this state. this input?s threshold has substantial hysteresis so that a capacitor to gnd can be used to delay restart after the current limit is activated. after v enh is exceeded, one clock cycle elapses before n-gate and p-gate are enabled. en is pulled up to v dd through a 500-k resistor and is pulled down internally when the current limit is triggered. pin 2: stby has a function similar to en. the differences are that the en pin is unaffected, that the reference is still available, that bias currents are still present internally, and that this pin?s pull up current is present. this pin should be used to disable an application if the reference voltage is still needed. pin 3: soft-start (ss) this pin limits the maximum voltage that the error amplifier can output. a capacitor between this pin and ground will limit the rate at which the duty factor can increase during initial power up, during a restart when en or stby goes high, or after the current limit is triggered. a capacitor here can prevent an application from triggering the si9150?s current limit during startup. soft-start is pulled low if either en or stby is low. pin 4: compensation (comp) this pin is tied directly to the output of the error amplifier. the feedback network which insures the stability of an application uses this pin. comp settles low when either en or stby is pulled low. pin 5: feedback (fb) this pin is attached directly to the inverting input of the error amplifier. this pin is used to regulate the power supply? s output voltage. pin 6: reference (v ref ) the internal 2.5-v reference generator is attached to this pin through a 5- resistor. a 0.1- f bypass capacitor is needed to suppress noise. also note that the generator has an open emitter; it will not pull down. the maximum current that the generator will source before it current limits is about 10 ma. many parts of the ic use this voltage, so it is important not to overload the reference generator. pin 7: i sense this pin should be attached to the switched node (the drains of the application?s p-channel and n-channel mosfet s). if the voltage between v dd and this pin is more then 0.46 v while the p-gate is low, the current limit is activated. the current limit is relatively slow to prevent false triggering due to noise. activating the current limit causes en to be pulled to gnd. i sense may be operated from v dd + 2 v to gnd ? 2 v. for operation above 13.5 v dd a filter (1 k , 33 pf) is needed between the mosfet drains and the i sense pin; refer to figure 1. pin 8: sync this pin forces the clock to reset when low, and is also pulled low when the clock resets itself. thus if several si9150?s have their sync pins shorted together, they will be synchronized; the shortest duration clock will control the other clocks.
si9150 vishay siliconix document number: 70020 s-40752?rev. f, 19-apr-04 www.vishay.com 5 pin 9: c t a capacitor from this pin to ground is charged until it reaches 2.5 v, at which point the capacitor is rapidly discharged. the resulting sawtooth with about 1 v added is compared to the input voltage at comp to determine whether p-gate and n-gate should be high or low. the maximum recommended value for c osc is 200 pf (see typical characteristics). the capacitor?s charging current is controlled by pin 10, r t . pin 10: r t the ic applies 2.5 v to this pin, and the current is mirrored and applied to pin 9 while charging the capacitor. the minimum recommended value of r osc is 20 k (figure 1). pin 11: gnd since the si9150 has a high-side current limit, it is important that v dd track the voltage on the source of the p-channel power mosfet . for noise immunity, it is best to separate the logic ground from the power ground. the logic ground should be decoupled to v dd through at least a 1- f capacitor. the two grounds may be connected by a path that is long compared to the the path from v dd to the source of the application?s p-channel mosfet. pin 12: n-gate this pin is used to drive the application?s n-channel mosfet. when turning the n-channel mosfet off, the p-channel mosfet will not be turned on until n-gate is within a few volts of ground. this pin is low while either en or stby is low. pin 13: p-gate this pin is used to drive the application?s p-channel mosfet. the break before make circuitry for the p-gate is complimentary to that for the n-gate. this pin is high while either en or stby is low. pin 14: v dd this pin powers the ic. the connection between this pin and the source of the p-channel fet should be as short as practical. read pin 11?s description for bypassing suggestions. applications figure 1. typical application circuit si9150 11 12 13 14 2 3 4 1 8 9 10 5 6 7 5600 pf 0.039 f 3.32 k 220 pf 47 pf 1 f 200 pf 56.2 k +5 v 43 h 10mq060 1000 pf 14.7 k 33.2 k 33.2 k si9943 100 f (20 v) v in 100 f 1 k 33 pf v in
legal disclaimer notice vishay document number: 91000 www.vishay.com revision: 08-apr-05 1 notice specifications of the products displayed herein are subjec t to change without notice. vishay intertechnology, inc., or anyone on its behalf, assume s no responsibility or liability fo r any errors or inaccuracies. information contained herein is intended to provide a product description only. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in vishay's terms and conditions of sale for such products, vishay assumes no liability whatsoever, and disclaims any express or implied warranty, relating to sale and /or use of vishay products including liab ility or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyrigh t, or other intellectual property right. the products shown herein are not designed for use in medical, life-saving, or life-sustaining applications. customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify vishay for any damages resulting from such improper use or sale.
? all leads 0.101 mm 0.004 e d e b a 1 a h l c 0.25 (gage plane) 1234567 14 13 12 11 10 9 8 package information vishay siliconix document number: 72809 28-jan-04 www.vishay.com 1 soic (narrow): 14-lead (power ic only) millimeters inches dim min max min max a 1.35 1.75 0.053 0.069 a 1 0.10 0.20 0.004 0.008 b 0.38 0.51 0.015 0.020 c 0.18 0.23 0.007 0.009 d 8.55 8.75 0.336 0.344 e 3.8 4.00 0.149 0.157 e 1.27 bsc 0.050 bsc h 5.80 6.20 0.228 0.244 l 0.50 0.93 0.020 0.037 ? 0 8 0 8 ecn: s-40080?rev. a, 02-feb-04 dwg: 5914
document number: 91 000 www.vishay.com revision: 11-mar-11 1 disclaimer legal disclaimer notice vishay all product, product specifications and data ar e subject to change without notice to improve reliability, function or design or otherwise. vishay intertechnology, inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectivel y, vishay), disclaim any and all liability fo r any errors, inaccuracies or incompleteness contained in any datasheet or in any o ther disclosure relating to any product. vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. to the maximum extent permitted by applicab le law, vishay disc laims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, incl uding without limitation specia l, consequential or incidental dama ges, and (iii) any and all impl ied warranties, including warran ties of fitness for particular purpose, non-infringement and merchantability. statements regarding the suitability of pro ducts for certain types of applications are based on vishays knowledge of typical requirements that are often placed on vishay products in gene ric applications. such statements are not binding statements about the suitability of products for a partic ular application. it is the customers responsibility to validate that a particu lar product with the properties described in th e product specification is su itable for use in a particul ar application. parameters provided in datasheets an d/or specifications may vary in different applications and perfo rmance may vary over time. all operating parameters, including typical pa rameters, must be validated for each customer application by the customers technical experts. product specifications do not expand or otherwise modify vishays term s and conditions of purchase, including but not limited to the warranty expressed therein. except as expressly indicated in writing, vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the vishay product co uld result in person al injury or death. customers using or selling vishay products not expressly indicated for use in such applications do so at their own risk and agr ee to fully indemnify and hold vishay and it s distributors harmless from and against an y and all claims, liabilities, expenses and damages arising or resulting in connection with such use or sale, including attorneys fees, even if such claim alleges that vis hay or its distributor was negligent regarding the design or manufact ure of the part. please contact authorized vishay personnel t o obtain written terms and conditions regarding products designed fo r such applications. no license, express or implied, by estoppel or otherwise, to any intelle ctual property rights is gran ted by this document or by any conduct of vishay. product names and markings noted herein may be trademarks of their respective owners.
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